Flash electrically erasable and programmable read-only memories (EEPROM's) are a class of nonvolatile memory devices that are programmed by hot electron injection and erased by Fowler-Nordheim tunneling. FIG. 1 is a cross-sectional view of a conventional flash EEPROM memory cell. The cell 10 is formed on a substrate 12, having a heavily doped drain region 14 and source region 16 embedded therein. The drain and source regions typically contain lightly doped deeply diffused regions 18, 20, respectively, and more heavily doped shallow diffused regions 22, 24, respectively, embedded into the substrate 12. A channel region 26 separates the drain region 14 and source region 16. The cell 10 typically is characterized by a vertical stack of a tunnel oxide layer 28, a floating gate 30 over the tunnel oxide, an interlevel dielectric layer 32, and a control gate 34 over the interlevel dielectric layer.
One important interlevel dielectric material for fabrication of an EEPROM is an oxide-nitride-oxide (ONO) structure. One EEPROM device that utilizes the ONO structure is a floating gate FLASH EEPROM device, in which the ONO structure is formed over the floating gate, typically a polysilicon floating gate.
Generally, a flash memory cell is programmed by inducing hot electron injection from a portion of the substrate, such as the channel section near the drain region, to the floating gate. Electron injection carries negative charge into the floating gate. The injection mechanism can be induced by grounding the source region and a bulk portion of the substrate and applying a relatively high positive voltage to the control gate to create an electron attracting field and applying a positive voltage of moderate magnitude to the drain region in order to generate “hot” (high energy) electrons. After sufficient negative charge accumulates on the floating gate, the negative potential of the floating gate raises the threshold voltage of its field effect transistor (FET) and inhibits current flow through the channel region through a subsequent “read” mode. The magnitude of the read current is used to determine whether or not a flash memory cell is programmed. The act of discharging the floating gate of a flash memory cell is called the erase function. The erase function is typically carried out by a Fowler-Nordheim tunneling mechanism between the floating gate and the source region of the transistor (source erase or negative gate erase) or between the floating gate and the substrate (channel erase). A source erase operation is induced by applying a high positive voltage to the source region and grounding the control gate and the substrate while floating the drain of the respective memory cell.
Non-volatile memory designers have taken advantage of the localized nature of electron storage within the silicon nitride layer of the ONO layer and have designed memory circuits that utilize two regions of stored charge within an ONO layer. This type of non-volatile memory device is known as a dual-bit EEPROM, which is available under the trademark MIRRORBIT™ from Advanced Micro Devices, Inc., Sunnyvale, Calif. A dual-bit EEPROM is capable of storing twice as much information as a conventional EEPROM in a memory array of equal size. A left and right bit is stored in physically different areas of the silicon nitride layer, near left and right regions of each memory cell. Programming methods then are used that enable the two bits to be programmed and read simultaneously. The two bits of the memory cell can be individually erased by applying suitable erase voltages to the gate and to either the source or drain regions.
Generally in the semiconductor industry, there is a continuing trend toward higher device densities. To achieve these high densities there has been and continues to be efforts toward scaling down the device dimensions on semiconductor wafers. To accomplish such high device packing density, smaller and smaller feature sizes are required. This includes the width and spacing of such features. This trend impacts the design and fabrication of non-volatile semiconductor memory devices, including the dual-bit EEPROM. For example, photolithography steps for patterning the floating gate and control gate of a small-scaled dual-bit EEPROM are particularly difficult and may reduce device yield.
Accordingly, it is desirable to provide a non-volatile semiconductor memory device that provides increased storage capacity with small feature size. In addition, it is desirable to provide a method for fabricating a non-volatile semiconductor memory device that provides increased storage capacity with small feature size. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.